Research And Design Of Cipher Specific Instruction Extension On RISC-V Processor

The hidden danger in the field of Io T is a security problem to be solved urgently.There are two encryption means of communication among IoT nodes: encryption by software or by custom algorithm module,but they have the disadvantages of low encryption performance and lack of flexibility.The cipher specific instruction processor based on RISC-V architecture has high encryption performance and good adaptability to different application environments.It can meet the information encryption requirement in the field of Internet of things.In this paper,we design a cipher specific instruction set based on RISC-V architecture.An extended instruction search algorithm based on instruction flow graph is proposed in this paper.Through the precise mathematical definition of instruction flow graph and subgraph,the extended instruction design is transformed into a graph theory problem of subgraph division.A subgraph-searching algorithm is designed based on simulated annealing,and the processing performance of the cipher algorithm is directly used as the optimization target,which integrates the function of subgraph screening into algorithm process and saves the workload of manual adaptation screening.The subgraph-searching algorithm is used to analyze 13 typical block and sequence cipher algorithms,analyze the characteristics of the selected subgraphs,determine the instruction implementation and hardware implementation of the subgraph.Design the format extension of the cipher instruction,and increase the upper limit of the single instruction throughput by setting the source-destination register and the register offset.On the basis of this,more than 40 extended instructions are designed,and a compact and efficient private cipher instruction set is constructed.A combined permutating module is designed to achieve subword shift and cascading shift operation according to the iterative characteristics of the permutating network.The permutation operation can be divided into several steps based on the amount of configuration information,so that the permutation instruction can be implemented in a RISC processor with limited single signal throughput.The vector storage structure is designed for the widely used vector memory access operation in the block algorithm.The traditional RAM is split to make each piece of RAM independent.It provides the hardware base for the Sbox operation in the cipher algorithm,and can exchange a small amount of storage space for significant performance improvement.Based on the RISC-V basic instruction processor,a cipher specific instruction processor is designed,a soft and hard cooperative processor testing environment is built,the function of the cipher specific instruction is verified,the acceleration ratio of the cipher instruction to the cipher algorithm is analyzed,and the logic synthesis is realized based on the 65 nm CMOS process library,and the performance of the processor is evaluated.The experimental results show that the application of cipher specific instruction designed in this paper can achieve the acceleration ratio of 5 to 8 times.The performance of the block and sequence algorithm of the cipher specific instruction processor can reach 226.34 Mbps and 55.55 Mbps,which can meet the communication encryption requirement in the field of Internet of things.