Digital Circuit Design And Implementation Of High Speed Serial Receiver Controller Based On JESD204B Protocol

With the improvement of modern information technology equipment,data converters are being forced to continuously improve their resolution,sampling rate,and bandwidth.This change has made conventional interface such as CMOS and LVDS unable to meet the transmission rate requirements of data converters and receivers(FPGA,ASIC)due to factors such as the limited transmission rate and power consumption.Therefore,the design of a serial transceiver that satisfies the high-speed transmission requirements of the data converter has become an urgent problem in the field of high-speed serial interfaces.In this situation,the JEDEC Association proposed a high-speed serial interface standard,JESD204 B,which has been widely used by foreign interface developers for its higher channel transfer rate,fewer pin counts,and lower system cost.However,the interface technology of China is still in the initial stage and there are no mature solutions.In order to meet the urgent needs of the market and seek breakthroughs in domestic interface technologies,this thesis designs a high-speed serial receiver controller based on the JESD204 B protocol.Its maximum channel transfer rate is up to 12.5 Gbps.Subclass 0 and subclass 1 mode,multi-channel synchronization,and configurable deterministic latency are supported.This thesis first describes the development process of the JESD204 series of protocols and compares the differences and improvements between the various protocol versions.Then a detailed analysis of the code group synchronization,initialization channel alignment,alignment code insertion and replacement,and deterministic delay of the JESD204 B protocol is performed.Based on the theoretical research of the JESD204 B receiver protocol,the architecture design of the JESD204 B receiver controller is proposed.A top-down design method was used to complete the design and simulation of each module of the receiver controller data link layer and transport layer.In addition,this design proposes a solution for on-chip testing,which makes it easy to perform functional tests on the sample after the tape.The JESD204 B receiver controller designed in this thesis has been taped using TSMC's 55 nm process and builting a test platform using the Xilinx KC705 development board based on the on-chip test solution.Finally,according to the relevant design indicators of the receiver controller,the test for each function of the sample are completed.Through the analysis of the test results,the high-speed serial receiver controller based on JESD204 B protocol designed in this thesis can correctly transmit data with the transmitter in the sample and the JESD204 B interface IP integrated by Xilinx,achieving a single-channel 10 Gbps serial transmission rate,subclass 0 and subclass 1 mode in the JESD204 B specification,multi-channel synchronization,and configurable deterministic latency in subclass 1 mode.