Research And Design Of High Performance Anti-SET PLL Based On 40nm CMOS Process

For a digital integrated circuit,it is inseparable from the reliable clock to realize various functions.Based on this,PLL is usually used to generate a stable clock.Therefore,it is necessary to design a high performance PLL.In addition,with the development of China's space industry,stringent requirements have been put forward for the design of integrated circuits.This is mainly because the space environment has a major impact on integrated circuits.This article for the actual needs of engineering completes a set of anti-SET PLL design for the DSP to provide a stable clock based on 40 nm CMOS technology.For the impact of SET on the phase-locked loop,the laser experiment was conducted to verify.According to the bombardment of different positions to determine the impact of each module,and ultimately through the data processing and analysis,observed that the impact of PFD on the phase-locked loop is increased jitter.DIV,on the other hand,results in the loss of lock and irreversible recovery.The VCO has some phenomena such as increased jitter,loss of lock recovery,and loss of lock recovery.Then the working principle of each module of the PLL is analyzed.The problems needing attention and the common structure of each module are explained and compared.In addition,the anti-irradiation reinforcement method of each module is given based on the laser experiment.For the PFD,the phase-defining dead zone is described and eliminated by introducing a certain delay at the reset end.The reinforcement of the PFD is mainly through the improvement of the D flip-flop.Through simulation verification,the PFD can not only achieve normal Phase detection function and has good radiation resistance;For DIV,the working principle and design implementation of dual-modulus prescaler are introduced.The high-frequency part is reinforced by the use of a three-mode redundancy reinforcement method;various problems for the charge pump and commonly used implementation methods are performed,and then gave a specific implementation of the programmable charge pump,for the CP reinforcement method is mainly to strengthen the layout level,in addition to its function simulation;the VCO part is explained,and ultimately choose the ring oscillator,the delay unit selection introduces a crossover tube on the traditional symmetrical load structure to increase the recovery speed and simulate its performance.Finally,based on the 40 nm CMOS process,the overall design and implementation of the phase-locked loop is completed: The maximum locked frequency of the phase-locked loop is 3.125 GHz,the locking time is less than 2.5us,the root-mean-square jitter is 2.59 ps,the peak-to-peak jitter is 3.39 ps,the layout area is 478um*296um。...