Research On Device Model Based RF CMOS Technology

Based on scalable rules,the technology of IC circuits has reached nanometer level.With the shrinking of transistor sizes,the device characteristics have changed subtly.When the feature size of a semiconductor device based on RF CMOS technology falls below 100 nm,many effects will become more and more obvious.In addition,with the operating frequency increasing,the parasitic effects of the device are also enhanced.Most existing device models are mostly suitable for digital and low-frequency analog circuit design,which focus on the properties of devices with frequencies within megahertz and ignore many physical effects,such as DIBL.MOSFETs are the commonly used device in integrated circuit design,while the capacitance density of MOM capacitor increases with CMOS process decreasing,which is a great advantage.Therefore,the research of MOSFET and MOM capacitor modelling based on RF CMOS process is highly valuable.The thesis mainly studies the modelling of MOSFET and MOM capacitor.The scalable models of MOSFET based on 40 nm CMOS process and MOM capacitor based on 55 nm COMS process are proposed.Meanwhile,on account of kinds of parasitic effects introduced in high frequency,a new modelling method for device based on RF CMOS process with test structure is presented.To increase the model accuracy and extend the effective frequency band,the test structure and input/output interconnections equivalent circuit are also considered together to model the MOM capacitor.The capacitive and resistive parasitics are extracted from the low frequency measurements of the open structure directly.Tradition physical formulations are employed to have an initial determination of skin effect elements in the high frequency of the transmission line.The model topology and parameter extraction method is verified by the MOM capacitor with test structure in 40 nm RF CMOS technology.The main contents of this thesis are as follows:(1)Understanding the working characteristics and physical effects of MOM capacitance and MOSFET based on CMOS technology.Learning the physical structure of the device and understanding its parasitic topology.Studying the influence of model parameters on the model.(2)Studying the small signal model of MOSFET device based on CMOS technology.By characterizing the RF features of MOSFE,the scalable model of the devices was established.(3)Studying the RF scalable model of MOM capacitor.A new modelling method for device based on RF CMOS process with test structure is presented.The modelling method is verified by the MOM capacitor with test structure in 40 nm RF CMOS process.(4)Optimizing existing models.The existing hardware and software conditions in the laboratory were used for testing,extracting model parameters and model verification.