Deep Learning Accelerator Design And Implementation For EEG Classification On FPGA

In recent years,research on brain-computer interface technology(BCI)has been very active in both the field of medical rehabilitation and academia,and has become a cutting-edge technology that technology leaders pay attention to.Despite the prospects for the development of this technology,there are still bottlenecks at this stage.On the one hand,we need to make the system run efficiently and quickly under the premise of ensuring the accuracy of EEG signals classification.On the other hand,the technology also needs to be closely integrated with artificial intelligence(AI),by training artificial intelligence systems to enable it to analyze and process these complex EEG signals.Based on BCI technology,this study proposes an FPGA accelerator system that combines flexibility and reconfigurability for different convolutional neural network(CNN)structuresthrough feature recognition and classification of EEG signals generated by motor imagery(MI)andimplemented the acceleration system on the PYNQ development board.The work of this paper mainly includes the algorithm design of EEG signals processing and the implementation of the algorithm on the FPGA.In the traditional analysis method of EEG signals,a fast Fourier transform(FFT)is generally performed on the time domain signal to obtain its spectral characteristics.Then,for the frequency band of interest of an electrode,the power spectrum of the signal is estimated by calculating the square of the spectral mode.Finally,the power spectrum measurements of all the electrodes are brought together to form a feature vector for subsequent analysis,but using this method will destroy the spatial structural features that exist between the data.In this paper,in order to preserve the spatial topology of the data,the EEG signalswere processed into a series of two-dimensional images in continuous time as the inputs of the CNN to improve the traditional method.The specific method is as follows: First,the position coordinates of the electrode inthree-dimensional space are projected onto the two-dimensional plane by Azimuthal Equidistant Projection(AEP).When all the electrodes of the head are projected,a two-dimensional plane of the range of the electrodes on the cerebral cortex is obtained.At the same time,the three frequency bands of the frequency domain signal(θ(4-8Hz),α(8-13Hz)and β(13-40Hz))are used as the main information processing area.Taking one of the three frequency bands as an example,calculating the power measurements of the frequency band as a partial energy value of an electrode and traversing all the electrodes of the entire two-dimensional plane.Then,we used the Clough-Tocherscheme(Delaunary-based cubic equation interpolation)to interpolate the power measurements over the scalp andestimated the values in-between the electrodes over a 28 × 28 mesh.Repeat the above process for the remaining two bands,and different energy colors(which can be understood as different channels)are used to distinguish the energy maps formed by different frequency bands.Finally,the energy maps generated by the three frequency bands are superimposed together to form a three-channel image as the input of the convolutional neural network with a dimension of 3*28*28;In the design of the FPGA accelerator,applying the synchronous dataflow(SDF)model to an embedded systemwhich does not cause more off-chip memory operations.The data flow method is also used to dynamically adjust the parameters of each layer to improve the reconfigurability of the system.By configuring the IP cores of each layer separately,a 16-bit fixed-point CNN is finally implemented on PYNQ for EEG classification.In this way,the pattern recognition and classification work required by the workstation or the computing node server in the traditional EEG signal system is replaced by the FPGA-based system board.The volume of the EEG signal recognition system is reduced,and the portability and processing speed are greatly improved.In the validation of the study,the accuracy of the classification of motor imagery(MI)EEG signals for the left and right hands using the BCI Competition database and the time it takes to process the same batch of data on the FPGA using the ARM Cortex-A9 CPU and the designed FPGA accelerator were determined.In the network training process for EEGsignal classification,our algorithm shows a training accuracy that reaches 96%,and the test average accuracy reaches 80%,the accelerator increases the speed by 19 times compared with the dual-core ARM CPU on the PYNQ.This research overcomes the shortcomings of the prior art,using software and hardware co-programming andproviding a deep learning accelerator design and implementation for EEG classification based on FPGAwith low threshold,high flexibility and extensibility,providing a new solution for the development of embedded control systems based on EEG signal recognition.