Analysis And FPGA Application Of Polling System In Wireless Sensor Networks

Wireless Sensor Networks(WSN)is a cross application of Sensor,Computer and Wireless network technologies.It builds a bridge between the physical world and the information world through a series of reconfigurable infrastructure and large-scale distributed sensor nodes through sensing and modulus conversion technology.WSN has a five-layer protocol system,in which the data link layer is constituted by the sub-layer of media access control(MAC)and logical link control.The information of each sensor node collected in the physical layer is transmitted to the bus at MAC layer under the resource scheduling technology,which approves to directly affect the life and performance of WSN.Polling control mechanism of MAC protocol based on point coordination function plays an important role in allocating transmission media for business group,possessing good delay characteristics.In addition,WSN is a mission-oriented network with high redundancy centering on data monitoring and processing.The rate characteristic of integrated circuit is the key to the processing performance of sensor nodes.How to realize the efficient data transmission by optimizing the basic completely,threshold,limit service strategy under the conditions of limited resource in the asymmetric polling system,and how to meet the requirements of the expansion and universality of the polling system and deploy the network quickly,have become the hot research topics among people in various fields.The logic resources are inserted in FPGA,in which tasks are parallelly performed,and the logic description is allowed to modify online by users,without redesigning the PCB and updating the logic function.The design is flexible and fast.Therefore,it is often used as the master controller when setting up the platform of real-time communication networks.The polling system is designed and implemented based on FPGA,and the MAC layer protocols are studied by performance evaluation in this paper.The modular hardware circuits are designed according to principle of polling communication.Independent control of real-time data cache and on-demand sending of each node is carried out by using asynchronous FIFO soft core,the optimized channel control strategies of MAC layer in WSN,including the threshold strategy distinguishing busy and idle,prioritized hybrid polling strategy and two-level threshold strategy,are designed according to the actual quality of service(QoS)features through soft programming using the Verilog HDL language,and the goal of ensuring each node within the cluster to access network without competition is achieved through setting finite state machines and strictly controlling the state transition conditions and signal output,in which the timing logic and combinatorial logic are integrated to set up the finite state machine.The frequency characteristics are further improved on the basis of symmetric polling system,and it proves to have wider universality to process the diversified business on the asymmetric polling system.Finally,the function of the system is tested based on QUARTUS II with the excitation signal satisfying poisson distribution characteristics,the consistency between timing simulation diagram and scheduling rules is verified.The performance of the system is evaluated by calculating the characteristic parameters,like average queue length,average polling cycle and average delay,which have a high fitting degree with the theoretical values.This indicating that the optimized scheduling strategy has better system performance and the hardware system based on FPGA has higher application value for WSN business deployment.