Research On 3D NoC Low Power Mapping Method Based On Improved Genetic Algorithm

With the rapid development of nanotechnology and very large scale integration(VLSI)technology,integrate a large number of IP cores into a single chip will be a problem of system-on-chip(SoC).The NoC architecture has completely solved the problem faced by the SoC from the architecture.However,with the rapid increase in the number of IP cores,2D NoC faces a series of problems such as chip area,performance,bandwidth and power consumption.Therefore,the concept of 3D NoC has been proposed.3D NoC packages a number of NoC chips with 2D structure into a single chip in a 3D package,and the chips are mainly interconnected by through silicon via(TSV).Compared with 2D NoC,it has smaller area,shorter delay,and has been greatly improved in terms of system performance and power consumption.Power optimization is an important part of NoC design.In this dissertation,power optimization is the main goal.In order to solve the problem of mapping IP cores to NoC reasonably,an Improved Simulated Annealing Genetic Algorithm based on initial population optimization is proposed.Firstly,the initial population selection method is improved to obtain a lower power consumption mapping scheme.Secondly,aiming at the randomness of its selection method,an improved roulette selection method is proposed,through the improvement of roulette selection,the possibility of selecting the optimal individual is maximized.Finally,for the local optimization problem of the genetic algorithm,the simulated annealing algorithm is combined with the genetic algorithm cross-operation stage to obtain the global optimal scheme.The experiment is implemented in C++ language under Windows system,the experimental results show that compared with the traditional genetic algorithm,the algorithm has better convergence and can quickly search for better solutions,in the case of 124 IP cores,the proposed method can reduce 32.0% compared with the genetic algorithm.