Research On Design Method Of Convolutional Neural Network Accelerator Based On RISC-V Open Source Processor

In recent years,along with the development of deep learning,the hardware acceleration of Convolutional Neural Network(CNN)has gradually become a hot issue in research.The combination of reconfigurable accelerator and general-purpose CPU has both versatility and optimization for specific problem scenarios,and becomes a solution to efficiently solve the acceleration problem of convolutional neural networks.However,on the one hand,commercial CPUs are increasingly expensive in patent licensing.On the other hand,the development processes of commercial CPUs and accelerators are not compatible with each other,and problems such as complicated development processes are encountered.Therefore,the mode of open source processors and accelerators represented by RISC-V Combined with a fully automated design approach,it helps to design CNN accelerated platforms more efficiently.To this end,this paper presents a RISC-V open source processor-based convolutional neural network accelerating structure and hardware design.In this paper,Eyeriss structure with better overall performance is selected as the basis for the analysis of existing accelerator structures such as Adder tree structure,pulsation array structure and Eyeriss structure.After that,there are four levels of research in paper: within a single Process Element(PE),PE Array structure,the parallel between the PE array,system hardware and software division.In a single PE level,in order to reduce the movement of data inside the PE unit,this paper adopts the way of maintaining circular array pointer to improve the operation efficiency inside the PE unit.At the PE array level,aiming at the problem that the Eyeriss structure easily causes waste of PE resources at the later stage of CNN operation,this paper proposes a size-adaptive acceleration structure,which effectively improves the PE resource utilization rate.The network has accelerated,and it has also been optimized for different Stride situations that may exist in different networks and convolution layers.In the aspect of parallelism between PE arrays,this paper makes use of the idea of mixed input and output parallelism,analyzes the requirements of bandwidth,cache and so on for parallel structures based on input and output features,and finally designs the network structure without changing 2 × 1 × 2 parallel acceleration structure,while controlling the memory bandwidth to improve the acceleration effect.In terms of system software and hardware,in order to improve the flexibility of the design of this paper,the control logic of the system is properly divided,and the adaptability of the system to different network structures is improved.This paper simulates the design in the Rocket-Chip Emulator,and simulates and synthesizes in the Vivado software.The test results show that the number of cycles in the forward flow is reduced to 19.46% of the serial in the case of this paper.Compared with the ordinary Eyeriss structure,the effect of this paper is improved by 22.3%.After introducing the parallel structure of I / O feature map,the number of cycles of a figure before the completion of the process is reduced to 11.6% of the serial structure.Compared with the common Eyeriss structure,the effect of this paper is improved by 13.01%.The experimental results verify the effectiveness of this structure in accelerating the convolution neural network,and the comprehensive results also show that the consumption of hardware resources is within an acceptable range.