0.3-3GHz SOI CMOS Low Power Down-conversion Mixer Design And Implementation

SOI(Silicon-On-Insulator),that is,silicon on an insulating substrate.This technology is to add a layer of buried oxide between the top layer of silicon and the back substrate,eliminating the latch-up effect of bulk silicon devices,with anti-radiation,small parasitic capacitance,high temperature resistance,high integration density,high speed and short channel The advantage of small effect.The down-conversion mixer converts the RF signal at the receiver's RF front-end to a baseband signal whose performance directly affects the performance of the RF receiver system.Therefore,using SOI CMOS technology to design broadband low-power down-converting mixer has a good engineering background and application value.The thesis designs a 0.3~3GHz wideband low-power down-converting mixer using a 0.28μm SOI CMOS process.The down-conversion mixer uses a pseudo-differential structure to improve linearity based on a double-balanced Gilbert circuit and uses current multiplexing to increase the conversion gain of the mixer and reduce its noise figure and power consumption.The thesis gives the circuit design,pre-simulation,layout design and post-simulation,as well as the tape-out and testing.The test results show that under the 1.8V power supply voltage and 0.3~3GHz operating frequency,the power consumption of the down-converting mixer core circuit is about 1.08 mW,the voltage conversion gain is 15.64~16.95 dB,and the input 1dB compression point is-9.36~-6.84 dBm,noise figure range is 9.14~11.06 dB,isolation is-84~-109 dB.In this thesis,the down-conversion mixer meet all performance requirements,operating frequency bands can be widely used in a range of narrowband or wideband 0.3 ~ 3GHz wireless communication system.