Research And GPU Implementation On LDPC Parallel Decoding Algorithms For DVB-S2 Standard

Low Density Parity Check code(LDPC)has Shannon-limit-approaching performance,and it has the characteristics of high-speed encoding and decoding.LDPC code has been used in many high-performance communication systems.And it also has been selected as data channel coding schemes in 5G standard's Enhanced Mobile Broadband(eMBB)scenario.In the research field of LDPC code,the implementation of decoder has always been a key and difficult problem,and it usually uses Field-Programmable Gate Array(FPGA),Central Processing Unit(CPU),Very Large Scale Integration(VLSI)and so on as the implementation scheme.In recent years,the intensive computing capability of Graphics Processing Unit(GPU)has made it rise in the field of general purpose computing.Computer Unified Device Architecture(CUDA)is a software and hardware architecture used to support general purpose computing on GPU.The CUDA's parallel architecture is very suitable for the implementation of high-speed LDPC decoder.Compared with FPGA,CUDA has many advantages,such as better programmability,more flexible and reconfigurable architecture,etc.Therefore,LDPC parallel decoder based on CUDA platform has gradually become a new research hotspot.The Digital Video Broadcasting Satellite-2nd Generation(DVB-S2)has excellent communication performance.It uses LDPC code as the inter code,and supports 21 code rates.Its code length is 64800 bits for long frame and 16200 bits for short frame.By taking DVB-S2 LDPC codes as application scenario,this thesis studies the scheme of LDPC parallel decoder based on CUDA and the available acceleration potential.Firstly,this thesis studies the CUDA platform and key technologies of CUDA programming model,and introduces some programming optimization strategies.Then,the LDPC coding and decoding theory and algorithms are studied and analyzed.The Bit Error Ratio(BER)performance of Belief Propagation(BP),Min-Sum(MS),Normalization Min-Sum(NMS)and Offset MinSum(OMS)Algorithms is compared and analyzed on the LDPC serial decoding simulation platform.Subsequently,the full parallel architecture decoder of several decoding algorithms(LLR-BP,MSA,NMSA,and OMSA)is implemented on the platform of CUDA.The implementation method of key modules and the storage mode of check matrix in this decoder are explained in detail.Finally,the serial and parallel decoding simulation platforms of LDPC codes based on DVB-S2 standard are compared.The experimental results of BER performance and decoding convergency are also given.The results show that the parallel decoder implemented on CUDA in this thesis can greatly reduce the decoding lantency,without loss of BER performance,and the maximum acceleration ratio can reach 17 times.It also proves that the parallel decoder implemented in this thesis can cover all code rates of DVB-S2 standard.