Energy-efficient AES Circuit Design For IoT Applications

With the continuous development of the Internet of Things(IoT)and system-on-chip(SoC),the requirements for the IoT chips to be considered in the design are constantly increasing,and data security is one of them.Due to the large number of information interactions in the Internet of Things,the encryption circuit is needed in the node of the IoT.The AES algorithm is one of the most commonly used block cipher algorithms.However,the area and power consumption of traditional 128-bit datapath AES are too high to meet the needs of lightweight devices.The 8-bit AES circuit proposed in recent years has reduced power consumption and area by changing the datapath from 128-bit parallel processing to 8-bit serial processing,but at the same time greatly reducing throughput.As a result,there are still two major challenges for 8-bit AES in reducing the area and improving the throughput when facing IoT applications.Therefore,this paper presents an AES circuit implementation and energy efficiency optimization for IoT applications.Two 8-bit datapath AES circuits are designed and implemented.Firstly,a single S-Box AES circuit for area-optimized is designed.Replacing the traditional look-up table S-Box core with an affine transformation S-Box core to reduce the power consumption and area,optimizing the execution steps of key expansion module and data encryption module and the number of intermediate registers to increase the throughput and reduction area,the entire AES operation implemented in 213 cycles.Secondly,a double S-Box AES circuit for throughput-optimized is designed,using 11 cycles to implement the key expansion and data processing module and fully utilizing the characteristics of the two parallel executions,implemented AES design in 113 cycles.Thirdly,a DPA attack for 8-bit AES is proposed.When the number of attacks is 3681,the correct key is revealed.Based on this attack method,a protection method for 8-bit AES is proposed.Discrete time points and random data encryption methods are used for S-Box cores.Implement 8-bit AES and protection scheme on the Spartan-6 XC6SLX75 FPGA,and finally achieve80,000 uncompromised effects.Finally,all-digital VCS simulation is used,and the entire design is verified by using the layout delay of the SDF file after the layout is done.The whole chip of the two 8-bit AES circuits is designed from RTL to layout using TSMC 28nm CMOS process.Under low voltage(0.5V),the maximum operating frequency of the two designs in this paper is50MHz,and the layout area is 0.0028 and 0.00309mm~2,respectively.Comparing the two designs with the traditional 8-bit AES circuit,the area gains reached 42.08%and 36.27%.Simulation results show that at low voltage,compared with the traditional 8-bit AES circuit,power consumption gains reach 37.15%and31.91%.And the energy efficiency area ratio of the two designs in this paper reaches 0.278 and 0.374Gbps/(W*?m~2),which is superior to other AES implementations.In summary,the two designs proposed in this paper can effectively reduce the area of 8-bit AES circuits and improve energy efficiency.