Ultra-low Voltage SRAM Design Based On Bit-Interleaving Architecture

Ultra-low voltage circuit designs for effective power reduction are widely introduced in Internet of Things(IoT)applications,such as wireless sensor networks and implantable devices.Therefore,ultra-low voltage SRAM designs are needed for these decices to reduces power consumptions.Although scaling down the supply voltage drastically reduces the power consumption,it degrades the SRAM cell read stability and write ability,and even causes read and write errors.On the other hand,with the scaling of supply voltage,soft errors become more pronounced.In order to enhance soft-error immunity of SRAM design for ultra-low voltage operations,a bit-interleaving architecture is normally employed combining with error correction code(ECC)technique.However,when a bit-interleaved structure is used,a half-select disturb issue appears,which will reduce the stability of the half-selected cell and limit the further reduction of the supply voltage.In addition,the read bit-line leakage current has also become a major problem at ultra-low voltage.It affects the swing of bit-line and even causes read failures.Therefore,it is important to design a high stability SRAM cell that can be used in a bit-interleaved architecture.First of all,we outline the challenges of ultra-low voltage SRAM design,including the cell stability,read bit-line leakage current and soft error.Secondly,according to the exist solution,we propose a novel ultra-low voltage SRAM cell that suits for bit-interleaving architecture.The structure and working principle of the proposed cell are introduced in detail.To evaluate the performance of proposed SRAM cell,we use HSPICE simulations to compare the SNM,WM,write/read access time,power,and other important performances for the proposed SRAM cell and the other SRAM cells in a 40-nm standard CMOS technology.The experimental results show that the proposed SRAM cell has high read stability and write ability.At a 0.4V supply voltage,the RSNM and WM of the proposed SRAM cell are 19.8× and 19.8× that of conventional 6T SRAM cell,respectively.Considering the worst process and the 3σ failure probability,the minimum operation voltage of the proposed SRAM cell is 0.435 V.In addition,it consumes less dynamic and leakage power,and its leakage power consumption is reduced by 53.3% when compared with the conventional 6T cell.Finally,we design a 4kb SRAM circuit and draw a corresponding layout in a 40-nm standard CMOS technology.According to the simulation results,at a 0.435 V voltage,the operation frequency is 9.3MHz at 25°C and TT corner.The read and write power consumption are 4.08μW and 3.85μW,respectively.The leakage power consumption is 0.705μW,and one write and one read energy consumption is 0.853 pJ.