Design And FPGA Implementation Of Memory Reduced Turbo Code Decoder Architecture Based On The Reverse Recalculation And Linear Estimation

Turbo codes,the major focus of channel coding,have attracted extensive attention in wireless communication system due to its excellent error correction capability.Nowadays,Turbo codes have been widely used in satellite communication,deep-sea communication,military communication and industrial internet of things.Meanwhile,Turbo codes have been adopted by the fourth-generation mobile communication system.Decoder is considered as the main bottleneck of power dissipation for signal receiving terminals in wireless applications,which apply Turbo codes to this domain.Due to the special properties of the decoding algorithm,more than half of the power dissipation of the decoder is primarily used for accessing the State Metric Cache(SMC)in the hardware implementation of the decoder.Therefore,in order to satisfy the requirements of high performance and low power dissipation wireless communication,the design of a low power dissipation Turbo decoder that reduces SMC capacity has become an important research.This thesis takes the Turbo codes in LTE-Advanced standard as the coding scheme for research.Firstly,the principles of encoding and decoding of Turbo codes are briefly introduced.Then,the maximum a posteriori probability(MAP)algorithm and its improved algorithm are deduced in detail,and the complexity of each algorithm is compared.The effects of different decoding algorithms on the decoding performance of Turbo codes are analyzed by simulation,which provide a theory for the selection of decoding algorithms.Next,the decoding scheme based on reverse recalculation is studied.Based on the correction of the Jacobian function,the scheme reduces the storage of the forward state metric by inserting a reverse recalculation module into the conventional Turbo decoder to reduce the use of SMC capacity.Compared with the traditional decoder architecture,the results show that the design makes the SMC capacity reduced by 50%.Then,inspired by the reverse recalculation design idea,this thesis proposes a Turbo decoder architecture for linear estimation of the forward state metric to further decrease the SMC capacity.The SMC capacity reduces by 55% by linearly processing the forward state metrics.In the above two types of Turbo decoder architecture,the power dissipation of the decoder is reduced by decreasing the use of the SMC capacity,but the SMC capacity can be further reduced.The decoder architecture based on linear estimation scheme has poor decoding performance due to excessive compression of state metric.Therefore,combined with the design idea of transformation method and reverse calculation,this thesis proposes a design scheme for linear estimation and reverse recalculation of state metric.In the traditional decoder architecture,incremental calculation module and linear estimation module are inserted to store half of the forward state metric,while the inserted reverse recalculation module completes the reverse recalculation of the other half of the forward state metric.The proposed decoder architecture scheme reduces the use of SMC capacity by 65%,and the performance of bit error rate(BER)and packet error rate(PER)is close to that of the maximum a posterior probability algorithm in logarithmic domain(Log-MAP).Based on the further discussion of the decoder architecture design,the various functional modules of the decoder are programmed by using the Verilog Hardware Description Language(HDL)in the Quartus II.The PowerPlay Early Power Estimator is used for power dissipation testing.The resource usage and power dissipation of the whole decoder architecture are analyzed.Compared with the traditional decoder architecture,the total memory of the decoder architecture is reduced by 35.62%.In addition,dynamic storage capacity power dissipation is reduced by approximately 50%,while the overall power dissipation of the decoder architecture is decreased by 4.97%,8.78%,11.93%,14.18%,14.65% at the frequency of 25 MHz,50MHz,75 MHz,100MHz,125 MHz,respectively.The results show that the power dissipation of the decoder architecture is decreased effectively.