SIPI Design And Analysis For LPDDR4x On 5G BB SOC

With the development of science and technology,we have entered the fifth generation mobile communication network era.Its theoretical peak transmission speed is tens of gigabytes per second,which is hundreds of times faster than 4G networks.Nowadays,the design of circuit is no longer simply using resistances,inductances and transistors.With the increase of the working frequency of the circuit,the transmission circuit signal is no longer ideal.When a certain degree of high frequency circuit noise,loss,power supply instability and other factors will make the voltage or current waveform distortion.Those can cause the receiver to misjudge the received signal,resulting in signal and power integrity problems.Therefore,in the era of communication network with low power consumption,high speed,high frequency and good stability,it will face more challenges to solve the problems of signal and power integrity in terms of data transmission and storage.In terms of memory,LPDDR4 X is a kind of DRAM memory and an updated version of DDR4 specification based on the fourth generation of DDR series.LPDDR4 X memory is increasingly favored by smart phone manufacturers.This thesis designs and analyses the SIPI of LPDDR4 X,a high-speed memory for baseband chip of 5G communication network SOC.In this thesis,the coordinated design and simulation of signal and power integrity of the system are carried out,from VRM to PKG,to baseband chip and finally to output board level.Firstly,a number of suitable decoupling capacitors are designed at PCB board level of PDN(Power Distribution Network)and placed at appropriate locations to reduce the characteristic impedance of power distribution network to an ideal value.Secondly,the PDN Modeling(PHY)model is designed on the baseband to make the whole PDN network complete.Thirdly,the current model of LPDDR4 X read operation is extracted,and the circuit model of LPDDR4 X write operation is designed by using bumps of "PCB + PKG" power distribution network as power supply and IBIS5.1 as drivers.Then,the following methods are used to analyze and optimize the write operation circuit: The deterioration of peak-to-peak noise increases by 10 m V when the clock resonant point is the same as the data resonant point by FFT;The peak-to-peak noise is reduced by about 20 m V by re-optimizing the circuit through the internal interconnection of the package layer;Through baseband PDN model and PCB power distribution network,the overall characteristic impedance of PDN is optimized again;The simulation results of original data rate 3733 Mbps and lifting data rate 4266 Mbps of write operation are compared and analyzed;Finally,the signal integrity of LPDDR4 X writing operation is designed by means of remote parallel terminal connection(terminal resistance is 60?),and compare the eye diagram results of time domain simulation before and after this operation.The eye diagram width of clock,dq0-8 and dq9-15 are improved from 380 ps,83.3ps and 82.3ps to 433 ps,181ps and 182 ps.Their signal jitter is improved from 114 ps,74.8ps and 75.3ps to 47.9ps,47.9ps and 47.1ps,all of which were greatly improved.The main highlights of this design: The PDN network enters the packaging layer and connects LDO in series,then passes through the packaging again and enters the PCB board,which reduces the occupancy of baseband space and power noise;The circuit design of the PDN network on the baseband makes the simulation data more precise,and the C_die value in the reference standard file is of practical significance;FFT simulation explores the deterioration of noise when the resonant frequency of clock and data mode is the same;Unique design of internal interconnection in PKG can significantly reduce the noise of power supply;The design of remote parallel terminal of signal integrity has greatly improved the signal eye diagram.The baseband chip of 5G network is relatively cutting-edge.At the same time,there are few researches on the collaborative design and analysis of LPDDR4X's signal and power integrity.Therefore,this thesis has certain practical significance,and to some extent,it supplements the blank of domestic signal integrity.