| In recent years,the process nodes of integrated circuit manufacturing have been advancing toward 14 nm and 7 nm.The complexity of chip design is growing,which cause overall power consumption and power consumption density increase dramatically,these could result in a decrease in reliability and stability of the chip.How to achieve low-power design goals in the new technology background is thrown into sharp focus.The design object is the signal processing CPU module in a baseband chip.The module has a scale of about 1.11 million gates and the highest frequency is 850 MHz.Based on the Intel 14 nm process,UPF based low power logic synthesis by Design Compiler and physical design by IC Compiler II are completed.Logic equivalence check by Cadence Conformal are done.Power analysis and power optimization by Power Compiler and Prime Time PX is performed during the synthesis and physical design stage.In this paper,the main results are as follows:(1)The power supply intention and lower power design requirements of the signal processing CPU module are introduced by UPF file.Firstly,the UPF based low-power synthesis is accomplished,then the timing,power consumption,and area results are assessed after the block synthesis is completed.Based on the results of low power synthesis,trade off the timing requirements,further power optimization is achieved: adjusting the ICG's fanout to reduce the power consumption by 1%;setting the reasonable timing over constraint to reduce the power consumption by 0.8%.The power optimization results in synthesis stage has shown that power consumption of the block under Ma Corner is further reduced from the original 34.1905 mW to 33.6575 mW,which is optimized 1.6%,the optimization effect is remarkable;the setup timing violation of the block is-64.9 ps,which is in acceptable range;area of the block reduced by 0.7% than before.Finally,logic equivalence check is done between the RTL and synthesis netlist.(2)Based on the optimized synthesis results,the physical design of the block is accomplished.During floorplan stage: the area and shape of the block are defined,IO plan is finished,the physical voltage area is divided,the hard macros are placed,the physical cells are inserted,and the power network is built;then standard cell placement,clock tree synthesis,post clock tree synthesis optimization,route,and post route optimization are completed.Finally,the logic equivalence check between synthesis netlist and layout netlist is done.(3)Four methods to further power optimization is applied during physical design stage.First,by using an optimized floorplan,power consumption reduced 7%;second,by optimizing the standard cell placement,power reduced 5%;and third,by using SAIF file assist power optimization,power reduced 4%;fourth,by using Synopsys' AWP model in physical design,power consumption reduced 0.7%.After power optimization is done,the setup timing violation of the block is-79.537 ps,the hold timing violation is-207.944 ps,both of the violations can be fixed by iterations of timing ECO;the area of the block is distributed by top level and stay the same during the power optimization stage;according to the power optimization result,the power consumption in Mrv corner reduced from original 71.5 mW to 61.6 mW with the four methods all used,which is optimized 14% and the effect is remarkable.At present,the chip has been successfully tape out in September 2018,and currently in testing.The synthesis and physical design methods in this paper has certain reference value for backend chip design which require high performance and use advanced nodes.The power optimization methods used in this paper has a certain range of applicability for the power optimization during synthesis and physical design stages. |
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