Design And Research Of N-Channel Enhanced Lateral RF Power Devices

As the core device of power integrated circuits,radio frequency LDMOS devices have become the research hotspot of many researchers in the field of device research at home and abroad.At present,the main technical difficulties lie in taking into account the characteristics of high integration,low power consumption,high gain and breakdown voltage.So the research direction of RF devices is mainly focused on designing and manufacturing more excellent and perfect RF power devices,that is to say,the lower the attack consumption,the better the device has higher voltage resistance and higher working frequency.In this paper,two new types of RF LDMOS devices are proposed,one is single-layer Shield source field plate RF LDMOS device and the other is partial step PSOI structure RF LDMOS.Firstly,on the basis of single-layer Shield source plate,the thesis designs and models RF LDMOS devices:the trench sinker structure which can reduce the area of the device is adopted in the active region of the source,and part of ladder PSOI structures are used as substrates to improve the structure by adding step gate structure.Under the conditions of voltage withstand,threshold and frequency characteristics that RF LDMOS devices need to satisfy,ISE-TCAD is used to simulate and compare the main parameters,such as the thickness and length of step gate,the length and concentration of drift zone,the thickness and length of shield field plate.The breakdown voltage,transfer characteristics,output characteristics,parasitic capacitance and frequency characteristics,which vary with the structure parameters are obtained.Finally,the optimal structural design parameters are given to reduce parasitic capacitance of the device to improve the frequency performance.That is,the LDD region injection concentration is 2 x 10¹⁷cm-3,the gate length is 0.5μm,the gate edge thickness is 0.08μm,the length of the LDD region is 5.5μm,the Pbase region injection concentration is 1 x 10¹⁷cm-3,the thickness and length of the shield are 0.4μm and 1.5μm,respectively.The breakdown voltage is 109V,the threshold voltage is 2V,and the gain is17.3dB at the operating frequency of 2450MHz.The breakdown voltage is increased by 49V and the gain is increased by 2.3 dB.Secondly,another improved method is simulated.The trench sinker structure and part of the stepped PSOI structure are also used as the substrates,and the stepped drift region is added to them as the improvement method.The voltage withstanding ability of Step-Doped LDMOS mainly depends on the length of the drift region and the total impurity mass contained in the unit area of the drift region.Using the simulation tool ISE-TCAD,the structural parameters were simulated and compared,including the concentration of Pbase region,the length and concentration of shallow doping and heavily doped LDD region,and the junction depth.The specific parameters which are most suitable for demand design are determined.That is,the injection concentration of Pbase area is 1.8 x 10¹⁷cm-3,the gate length is 0.5μm,the length of the LDD area is 1.5μm for the light doping part,the length of the heavy doping part is 2.5μm,and the concentration is 2 x 10¹⁷cm-3 and 4 x 10¹⁷cm-3,respectively.The junction depth is 0.5μm and 1μm respectively.The technical specifications met at this time are the breakdown voltage of 65V,the threshold voltage of2V,and the 19dB gain at the operating frequency of 2450MHz.