Study On The Structure Optimization And Reliability Of Resistive Random Access Memory (RRAM) Based On Tantalum Oxide

In recent years,with the development of cloud storage,internet of things,artificial intelligence,the storage devices are facing the requirements of high performance,low cost and high integration.On the other hand,with the shrinking of semiconductor process nodes,the Flash memory shows the weaknesses,including the low operation speed,high programming/erasing voltage and high power consumption,which greatly limits its application.Recognizing this,the researchers have done extensive research into the next generation of non-volatile memory technology.Resistive random access memory(RRAM)is considered as the most promising new storage technology due to its simple structure,low power consumption,good reliability,low manufacturing cost and good CMOS compatibility.Although the researchers have researched on the materials,mechanism,and reliability of RRAM for many years,there are still some challenges before the realization of commercial applications,such as the uniformity of the devices,the reliability issues and read disturbance and so on.Focusing on these issues,we proposed the multilayer structure and two optimized programming strategies to develop the device.Finally,the integration verification was carried out on the 40 nm process platform in UMC.Firstly,the resistive memory based on tantalum oxide is designed to be compatible with the standard CMOS logic process.For the uniformity issue,we introduced the buffer layer structure to adjust the extraction and injection of oxygen ions effectively during the set/reset process.After reducing the number of defects caused by overprogramming,the uniformity of device parameters is improved.Secondly,we established the failure model based on the degradation behavior of the endurance.During the programming,the formation and rupture of conductive filaments is a transient processes,which is easy to produce more uncontrollable oxygen ions.The accumulation of oxygen ions leads to the device degradation.Based on this understanding,we proposed the third-level-pulse operation scheme to push the oxygen ions move step by step,and the control the morphology of the conductive filament more accurately.By adopting this scheme,the endurance of the device is improved by 100 times.Thirdly,we studied the read disturbance of the RRAM.During the erase process,the excessive energy will produce too much oxygen vacancy defect in the device.The spontaneous trap/de-trap behavior of ions in the oxygen vacancy caused the resistance fluctuation during the reading process.For this reason,we proposed a multi-pulse programming scheme in the erase process to reduce energy consumption by 1.7 times.Thus the read disturbance of devices is improved due to the reduction of the number of defect states.Based on the optimized device structure and programming scheme mentioned above,we conducted integration verification on the UMC CMOS 40 nm process platform.The devices show the good uniformity and reliability.This proves that the above results have guiding significance for the realization of industrial application of RRAM.