Research And Implementation Of Physical Downlink Shared Channel Demodulating Link For 5G Terminal Simulator

With the commercialization of 5G technology,5G system has been integrated into almost every aspect of our life.As a new generation of communication network,5G network owns higher transmission rate,more various application scenarios and more intensive connecting devices.Nowadays,there are more and more terminal simulation schemes for 5G network,but there is a lack of solutions in environmental diversity and system stability,and the products and equipment of international communication manufacturers still have certain advantages.Due to the problems of single equipment function,immature underlying technology and high development cost embedded in the design of terminal products produced by domestic communication manufacturers,the research and development of 5G terminal emulator is particularly important.Based on Chongqing's major project "Development and Application of Network Testing Technology for New Mobile Communications",this paper combines 5G technology,R15 protocol standard and various existing algorithms to study the data processing of downlink shared channel of terminal simulation system.And both Matrix Laboratory(MATLAB)and Field Programmable Gate Array(FPGA)are used to design and implement the process of demodulation and Cyclic Redundancy Check(CRC)of the downlink shared channel.The main innovations and work contents are as follows:1.In order to solve the influence of channel signal-to-noise ratio on 256 Quadrature Amplitude Modulation(256QAM)high-order modulate demodulation technology,through the calculation of mutual information in bits and under the condition of not affecting the total mutual information,the bits with smaller amount of information should be deleted,and the remaining bits could be demodulated,so as to improve the average mutual information of bits entering the decoder and the effect of reducing decoding complexity can also be achieved.2.In order to solve the problem that the decoding process of Low-Density Parity-Check(LDPC)codes takes up system resources and so on,the decoding performance of serial and parallel decoding modes are analyzed,the layered parallel decoding scheme is studied,the advantages and disadvantages of Normalized BP-based algorithm and Offset BP-based algorithm are compared,and the Normalized BP-basedalgorithm with normalization factor ? is finally determined to be more suitable for LDPC decoding of this topic.3.In order to improve the system performance in the verification process,CRC serial algorithm and parallel algorithms are studied.Based on the hardware requirements,a kind of CRC check algorithm that combines the serial and parallel decoding modes is proposed to check the decoding results by comparing the consistency of previous and subsequent CRC check codes.The simulation of various process modules and the overall test results show that under the condition of adhering to protocol standard,the total time consumed by the flow scheme of Physical Downlink Shared Channel(PDSCH)demodulation scheme is0.519 ms,and the system bandwidth is set to 20 Mbit to 100 Mbit,each module meets the design requirements.Therefore,the PDSCH demodulation scheme proposed in this paper meets the performance requirements of 5G terminal simulation system in general.