Research And Design Of Subpixel Rendering Algorithm For AMOLED Driver IC

With the increasing resolution of AMOLED(active matrix organic light emitting diode)and the limitation of pixel processing technology,the arrangement and number of sub-pixels have changed.The sub-pixel rendering circuit in the AMOLED display driver can convert the standard image data transmitted by the host processor into gray scale data conforming to the arrangement of sub-pixel on the AMOLED panel,so as to restore the correct image information on the AMOLED panel.Sub-pixel rendering circuit has become an important part of image processing in high-resolution AMOLED display driver.In this paper,aiming at 1080 × 2160 RGB delta sub-pixel arrayed AMOLED panel,the architecture of image processing module in display driver and hardware circuit of sub-pixel rendering algorithm applied in image processing are designed.First of all,the principle of OLED and the realization of pixel color are investigated and analyzed,and the digital system architecture and data transmission timing of drive circuit are studied in detail.Secondly,this paper studies and compares the RGB delta sub-pixel arrangement and other AMOLED panels,and proposes the rendering principle of sub-pixel rendering algorithm according to the characteristics of panel arrangement.On this basis,an algorithm of sub-pixel rendering weight coefficient based on threshold comparison is designed,which can avoid the color edge effect of image display.In this paper,the algorithm is simulated and verified based on MATLAB platform,the mean PSNR of random image is 40.45 db,and the point screen test is carried out on LCD and RGB delta AMOLED screens with standard subpixel arrangement,and the display effect is good.In this paper,Verilog is used to design the sub-pixel rendering algorithm circuit and SRAM read-write logic control circuit,and the cascade simulation is carried out.The sub-pixel rendering algorithm circuit mainly includes the control module to judge the received image data by parity row,the synchronous signal processing module,the data control module and the rendering operation module.In the process of data processing,four single port SRAM are used to form a ping-pong structure to realize the function of dual port reading and writing.The processed image data is output and driven according to the display timing of the driving circuit.In this paper,the model SIM simulation tool is used to verify the code function,and the results show that the function of each circuit module is correct.After DC synthesis of the front-end code,power planning,clock tree synthesis,wiring and other design steps,the GDS II layout of the sub-pixel rendering circuit is successfully generated in the umc80 nm process,and physical verification is carried out.Through the static timing analysis,the expected goal is achieved.