Research On Instruction Set Of Tile Architecture Based On Discrete Event Model

With the development of big data and cloud computing technology,there is a huge demand for various processors for specific scenarios and specific algorithms.Tile architecture processors are designed to improve the processing efficiency of dedicated instruction sets.The modular design of the Tile processor is simple,and easy to reuse.The shorter inter-chip wiring makes it easier to increase the operating efficiency of the chip than the general-purpose processor with a long wire centralized design.So it can be used in some cases to optimize the effect of performance.The Tile architecture processor has the advantages of high frequency,simple control logic,good scalability,easy implementation,lower power consumption,lower communication delay between modules,and shorter design and verification cycles.With the development of big data and cloud computing technology,the amount of data that needs to be processed is increasing drastically.The processor of the Tile architecture is a special architecture ushered in new development space.How to simulate and analyze the Tile architecture processor for a specific algorithm has become an important topic.The cost and efficiency of the processor directly affect the development of the Internet of Everything in the era of the Internet of Things,so it is of great significance to study this topic.In the era of big data and cloud computing,a large number of application requirements for high-performance processors for certain scenarios will inevitably appear.In order to promote the large-scale application of Tile architecture computers,a high-performance,parallel processor application solutions is proposed.The feasible simulation,analysis and verification methods for this kind of architecture processor are proposed.The main work of this thesis are as follows:1)This thesis uses the discrete queue model to simulate the instruction set and its tasks in the Tile structure.We study on the instructions and task queue allocation strategies,and analyze the advantages and disadvantages of various methods.2)This thesis constructs the mapping relationship between the instruction set of Tile architecture processor and discrete events.A discrete queue model based on Tile architecture processor is established.The interval time distribution of task is analyzed when the input process follows Poisson flow distribution.3)In this thesis,the discrete event queue model is used to simulate the instruction set block in Sim Events software.By comparing the server response time of different cache queues,differentprocessor core allocation methods,different scheduling strategies and different resource allocation situations the server's response time and task allocation situation,we verify the feasibility and effectiveness of the simulation and analysis method of the Tile architecture based on the discrete event model proposed in this paper.Our study is a foundation of the future work for the simulation,analysis and verification of Tile architecture.