Study On Address Translation Of Large-capacity Solid-state Disks

Flash solid-state disks have better performance than mechanical disks in the aspect of random access,and the development of flash memory technology has made the capacity of solid-state disks larger and larger.However,flash solid-state disks have to use flash translation layer to avoid the physical limitations of flash memory and address translation algorithm is one of the main functions achieved by flash translation layer.Page-level mapping algorithm has a good performance on random writes and its mapping table is easy to manage,and it also has a more positive effect on the average life of solid-state disks than block-level and hybrid level.Hence,page-level mapping algorithm is a mainstream choice.If large-capacity solid-state disks use page-level mapping,they have to keep a very large mapping table,but it is difficult to increase the capacity of RAM in the same proportion as flash memory.In order to reduce the RAM footprint of the mapping table,two mapping algorithm schemes are presented in this paper.One is based on a large granularity,and the other is a demand-based optimization scheme(DOPFTL).For the first scheme,it reduces the size of the mapping table by increasing the granularity,but may increase the write amplification.For the second scheme,it uses two ways to cache mappings and one of them uses extent mapping technology to compress mappings.In addition,it adopts fine-granularity management of mapping cache to make the space ratio of these two ways adaptive to workload.On the other hand,DOPFTL adds a new field in the global translation table,which helps to locate the location of mappings in the cache.Based on the above design,we conducted a simulation analysis on cache hit rate and delay of DOPFTL,DFTL and TPFTL,which are all page-level mapping algorithms.The results show that DOPFTL has a high cache hit rate which is 59% higher than DFTL,and have the delay reduction of 79% and 54% compared with DFTL and TPFTL.