Design And Implementation Of High Energy Efficienct Neural Network Hardware Based On Analog Delay

With the development and application of deep learning,deep neural network have played an important role in many fields.The increasing size of neural networks and the increasing complexity of computing will inevitably lead to the problem that is high energy consumption and low energy efficiency of network accelerators.Mobile communication devices often have requirements of low power consumption and high energy efficiency,which makes it difficult to apply accelerator chips to mobile communication devices.This paper adopts a binary convolutional neural network and completes the neural network accelerator design based on analog delay for the MNIST data set.To achieve the goal of low energy consumption and high energy efficiency.First,for the core computing unit of the accelerator,a computational array consisting of a low-power analog delay chain is substituted for the computational array of the same-gate and accumulation tree.Secondly,the calculation of the batch normalization layer is optimized,the hardware overhead and energy consumption is saved.Thirdly,an effective computational pattern is adopted to achieve effective data reuse and convolution mapping,and the utilization rate of the computational array reaches 100%.Finally,a pooling-based convolution sparse algorithm is proposed.It reduces the calculation cycle by 14.3%and the power consumption of calculations.Two accelerator chips are designed in this paper.The first chip is a binary convolutional network accelerator that uses analog delay chains、batch normalization optimization and computational pattern optimization.This design is taped out in TSMC 28nm CMOS library.The chip test is completed.The area of entire accelerator chip is 1.92×1.35mm~2.Measurement results show that the energy efficiency of the chip achieve 51.4-5.50TOPS/W with wide voltage range from 0.42V to 0.9V and operating frequency range from 25MHz to 500MHz.Another binary convolutional network accelerator chip uses a pooling-based convolution sparse algorithm on the basis of the first chip.This design is synthesized using TSMC 28nm CMOS library.The simulation results show that the energy efficiency of the chip achieve 97.4-13.8TOPS/W with the operating condition from 0.5V(25MHz)to 0.9V(500MHz).Compared with state of art of related designs,the proposed design has an excellent effect on reducing energy consumption and improving energy efficiency of neural network accelerator chip.