Research And Implementation Of Low-Complexity Algorithm For Parallel Equalization Of High-Order QAM Signal Demodulation

The constant pursuit of higher communication rates is an eternal theme for the development of communication systems.Quadrature Amplitude Modulation(QAM)has been widely used in the design and application of high bit rate communication systems due to its characteristics such as high spectrum utilization and strong anti-noise performance.This paper focuses on the equalization module of the QAM-based all-digital receiver under high demodulation symbol rate.Equalization technology is mainly used to combat the inter-symbol interference introduced by channel multipath effect and digital filter finite word length effect during signal transmission and optimize the transmission error rate of the communication system.The equalizer is an important module in all digital receivers.In order to meet the highperformance development requirements of single-link high-bit-rate QAM communication systems,data parallel processing technology based on fixed modulation order limits and realistic electronics device development levels is one of the most important solutions at present.Based on the theoretical analysis,the paper first carried out a theoretical analysis of receiver equalization based on high-order QAM modulation.Because the use of highorder QAM modulation will cause the distance of the signal constellation to become smaller,it is necessary to choose a channel equalization algorithm with a small steadystate residual error.Taking into account the computational difficulty and steady-state residual error performance of today's mainstream equalization algorithms,combined with the overall development requirements,the CMA + HCMA dual-mode algorithm was selected as the equalization algorithm used in this paper.This dual-mode algorithm has a small steady-state residual error,while the computational complexity is moderate and suitable for the parallel implementation architecture of this paper.The paper uses simulation analysis to analyze and verify the feasibility and effectiveness of the selected equalization algorithm scheme.MATLAB simulation results show that the CMA + HCMA dual-mode equalization algorithm can effectively equalize QAM signals with severe inter-symbol interference.And,by analyzing the steady-state residual error performance of the equalization algorithm,it proves that the algorithm is superior to the single-mode CMA algorithm,MMA algorithm and other common equalization algorithms in terms of steady-state residual error performance.The paper completes the FPGA engineering implementation module of the parallel blind equalization scheme for high-order QAM all-digital receivers.During the development process,the content of optimizing the resource consumption of the parallel algorithm is considered.The direct parallel implementation of the equalization algorithm based on LMS adaptive filtering will bring a lot of resource consumption.In order to ensure that the entire parallel blind equalizer structure can be implemented on an FPGA with a small resource scale,the paper studies the iterative short convolution algorithm(ISCA)and relaxed look-ahead technique of the parallel filter and designs a highly efficient implementation scheme of parallel adaptive filters,so that the parallel blind equalization algorithm in this paper can be implemented in FPGA modules with medium level resources.The paper builds a board-level test platform based on Kintex-7 series FPGAs,and verifies the feasibility and effectiveness of the parallel blind equalizer designed by the paper.The verification results show that the 8-channel parallel blind equalization module designed in the paper can be successfully implemented on Kintex-7 series FPGAs,and can smoothly equalize 64 QAM signals with inter-symbol interference.The convergence speed,the steady-state residual error and the equalization performance of the implemented parallel blind equalization module has meet the design requirements.