| Convolutional neural network(CNN,Convolutional Neural Network),as an important branch of artificial neural network,has been widely used in the field of machine vision.With the complexity and diversification of application scenarios,the requirements for the speed and accuracy of neural network algorithms have become higher and higher.Single-shot multi-box target detection algorithm(SSD)is a target detection algorithm proposed by Wei Liu on ECCV2016.As of now,it is one of the main detection frameworks.Compared with Faster RCNN,it has a significant speed advantage.Compared with YOLO,SSD customer service This makes it difficult to detect small targets and inaccurate positioning.Due to the problems of slow computation speed and high power consumption on general-purpose CPU and GPU platforms,convolutional neural networks can use hardware accelerators to greatly increase computing speed and reduce power consumption through computational data reuse,parallel design,and pipeline technology.As the scale and complexity of chip design continues to increase,the verification work becomes increasingly complex and important.The verification cycle has reached more than 70% of the entire chip development cycle.It is said that the correctness and stability of the chip's functional design are verified through verification An inevitable trend for chip development.This article first introduces the basic structure and characteristics of a convolutional neural network,and analyzes several internal calculation modes,including convolution,pooling,non-linearity,matrix multiplication,etc.,and provides a theoretical basis for later understanding of the hardware accelerator architecture.Then the article also analyzes the structure of the single-shot multi-frame target detection algorithm.Compared with the conventional convolutional neural network algorithm,what are its characteristics,the feasibility of mapping it to a hardware accelerator,and its advantages compared with traditional CPU operations are analyzed.In addition,this article also introduces several important concepts in Universal Verification Methodology(UVM).These concepts are the basis of UVM and are often used in subsequent verification work.Then this article analyzes the architecture of the convolutional neural network hardware accelerator.It focuses on four secondary sub-modules: data preparation module,convolution operation module,result processing module and post-processing module.They are designed from design requirements,parameters,interfaces,and system structure And sub-module design,and deeply understand the hardware accelerator's implementation of data preprocessing,convolution operations,pooling,and postprocessing operations in convolutional neural networks,analyze its data reuse methods and efficiency,and analyze dual data formats The advantages and difficulties of using int8 and float32 mixed precision multipliers save 312 8-bit multipliers and 312 16-bit adders.Using data reuse technology based on GeMM(General Matrix Multiply)algorithm makes the data reuse rate reach 100%.After gaining a deeper understanding of the design architecture,the verification plan was developed.First of all,for the core data preparation module in the convolutional neural network hardware accelerator,the test points are decomposed according to the corresponding design requirements and design documents.Construct special test cases for corresponding test points,complete test case planning,formulate verification strategies,set up verification platforms,simulate debugging,run test cases and collect coverage,so that the functional coverage reaches 100%.Complete module-level verification to perform system-level verification of the accelerator,covering all test points,training a single-shot multi-frame target detection algorithm to achieve an average accuracy of 0.697,and constructing a 3-layer test algorithm based on a convolutional neural network accelerator,at a 50 M clock Can recognize 6980 frames per second,achieving the expected goal. |
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