Network-on-Chip Traffic Reduction Method Based On Traffic Phased Behavior

The design process of network-on-chip(NoC)is to design a NoC architecture,then test and determine the bottleneck of the NoC,finally improve the NoC architecture.Injection traffic simulation is typically used to test and determine the bottleneck of the NoC.The mainstream injection traffic includes traffic patterns,dependency-based trace streams and real applications.There are advantages and disadvantages when using these three injection traffic for simulation.Traffic patterns simulation may result in inaccurate simulation results;dependency-based trace streams simulation is not easy to operate because it needs to be obtained in advance,but extracting trace is very tedious;real application simulation is time-consuming because the data is too redundant.The NoC traffic reduction method based on traffic phase behavior is to reduce simulation time by eliminating phase redundant data of real applications,thus ensuring the accuracy of test results.In the thesis,time interval is used for traffic segmentation.Each traffic segment first uses scales to represent the temporal behavior of traffic segmentation,and then uses vectors to represent the spatial behavior of traffic segmentation;Then k-means clustering algorithm is used to select representative traffic segments;Finally,Markov chain is used to connect these representative traffic segments.Because the flow is not constant,it has sudden onset in time,which makes the flow sometimes dense and sometimes sparse,so it can not use the same granularity of flow reduction method to deal with all traffic.In order to more accurately reflect the sudden flow,for those traffic sparse fragments,only the coarse-grained reduction method is used once;for those traffic-intensive fragments,fine-grained reduction is used for many times.Using different granularity reduction processing for different sizes of traffic,which can not only more accurately represent the whole flow operation process,but also improve the accuracy of flow simulation after using the reduction method.The traffic reduction method used in this thesis is verified separately in terms of accuracy and time.In terms of accuracy,the delay and throughput are verified separately.The delay is compared with the real application error of 8.6%~14.6%,compared with the dependency-based trace stream error of 3.6%~9.9%,which is compared in terms of throughput.The real application error is 7.3%~13.3%,compared to the dependency-based trace flow error of 3.2%~18.9%;In terms of time,the simulation acceleration rate is 20~30 compared to the real application simulation,compared to the dependency-based trace stream is 2~4.5.Using the reduced traffic of this thesis to test the NoC architecture can greatly reduce the simulation time to accelerate the development of the chip and shorten the time of the entire development cycle.