| Digital array radar can formate digital multi-beam flexibly and have the characteristics of large dynamic range and adaptive anti-jamming by using digital beamforming technology.Based on a 176-element digital array radar project,this paper designs a full-array IF sampling and digital multi-beamformer based on two-class architecture,completes the hardware architecture design and beamforming algorithm design of two-class beamforming,develops corresponding hardware circuit development and software development,realizes the functions of receiving digital multi-beam and transmit beamforming.The main work of this paper includes the following aspects:1.Designed a digital beamforming scheme based on two-class architecture,given the beamforming calculation method of 176-unit receiving channel in two-class architecture,the transmit beamforming algorithm and the calibration algorithm of receiving channel.2.Developed the hardware circuit of 176-channel IF sampling and the first beamformer,given the scheme of sampling,processing and synchronization,and completed the schematic diagram and PCB design.3.Designed the FPGA software of multi-channel IF sampling and first-class beamforming,including multi-channel AD sampling interface,wide-band and narrow-band multi-mode digital down-conversion with partial resource reuse,receiving multi-channel beamforming,transmit beamforming,high-speed data transmission and other functional modules,and completed the design,debugging and verification.4.Test the first-class IF sampling and beam preprocessing circuit,including the A/D Effective Number of Bits(ENOB),channel frequency response of narrow-band,receiving channel calibration function,the DBF function,and the pattern.The measured results show that:A/D ENOBs are not less than 10.8 bits;3 beams of40 MHz bandwidth,12 beams of 24 k Hz bandwidth and 3 beams of 4k Hz bandwidth can be formed simultaneously in receiving beamforming;1 transmitting beam can be formed in transmitting beamforming;and it has the function of receiving channel calibration.At the same time,digital down-conversion technology and digital beamforming technology with partial resource reuse are used to reduce the hardware computing resources of the FPGA. |