Design, development and simulation of sub-lithographic process for patterning nm scale features

The ability to create sub-lithographic nm-scale features without the need of high-end lithography tools will create new opportunities for the electronics industry. Most current technologies are lithography dependent and inherit associated CD variations.;The mainstay of this work is mathematical modeling, simulation and verification of a revolutionary void transfer process for patterning nm scale features originally introduced by Breitwisch et al. at IBM. The technique studied involves intentional creation of voids using a conformal chemical vapor deposition (CVD) followed by controlled etch-back to form nanoscale pores. This method provides features that are independent of lithographically defined parent holes and exhibit lower critical dimension (CD) variations. It offers efficient low thermal budget and backend process compatible integration scheme that requires just one additional mask level. To the best of author's knowledge no simulation study of the void transfer process has been reported in the literature so far. Thus, this project initiated scores of `firsts' towards the development of a reliable nano-patterning technique and a robust process infrastructure for future projects at RIT. The pores with diameter of 130 nm were obtained i.e. an impressive ∼7X reduction from lithographically defined hole of 714 nm using conventional i-line lithography. Critical parameters affecting the void formation and the final pore size have been identified and modeled. Simulation of the void transfer process has been investigated using plasma etch module of 'Elite' by Silvaco that employs 2-D Monte Carlo ion transport modeling. The results of this investigation show that the geometrical design parameters can be coupled with the plasma process simulations to develop an efficient module for the void transfer process.