Study of thermal fatigue of wafer level packages under temperature cycling

Solders are used extensively as electrical interconnects in microelectronics. Because of government regulations due to environmental concerns, lead based solders (SnPb) are being replaced by lead-free solder materials. One of the promising lead-free alloys is SnAgCu (SAC) (e.g. Sn96.5%Ag3.0%Cu0.5%). There are many challenges associated with reliability for lead free solders such as their melting temperature range, manufacturability, and mechanical performance under high temperature and high stress conditions. Therefore it becomes imperative to understand the fundamental behaviors of solder alloys. In this thesis, the Anand's model is used to describe the inelastic deformations of the solder alloys. The inelastic deformation includes both creep and rate-independent plastic deformations. Two typical Anand's models for SnPb and SAC have been introduced, respectively. Finite element analysis (FEA) is applied to a one-dimensional problem subjected to different temperatures and loads. Two solder alloys (SAC and SnPb) are analyzed simultaneously under different temperatures and tensile stresses. SnPb solder experiences less inelastic deformation than SAC at lower temperatures and stresses. But, SAC solder tends to creep less than SnPb at higher temperatures with a higher level of stresses.;Wafer Level Packaging (WLP) has the highest potential for future single chip packages because the WLP is intrinsically a chip size package. It is one of the fastest growing segments in semiconductor packaging industry due to the rapid advances in integrated circuit (IC) fabrication and the demands of growing market for faster, lighter, smaller, yet less expensive electronics products with high performance and low cost packaging. However, due to the mismatch of the coefficient of thermal expansion (CTE) between silicon and plastic PCB material, solder ball reliability subject to temperature cycling become the weakest point of the standard WLP technology. In order to improve the thermal cycling reliability, cu post WLP structure is developed. In this thesis the fundamental understanding of the cu post WLP reliability under thermal cycling is studied using 3-D finite element analysis. The finite element model considers all detailed structures of a cu post WLP, including redistribution layer (RDL), passivation, cu post, and epoxy. The energy dissipation per cycle at the critical locations is calculated based on the volume averaging over a thin layer of solder material along the solder ball and cu post interface. By assigning the material properties of cu post, passivation layer, and epoxy to the properties of the silicon, the cu post WLP becomes a traditional WLP without under bump metallurgy (UBM). Results showed that the energy dissipation per cycle for a cu post WLP is about 45% less than that of the modified cu post WLP. This implies that the introduction of cu post and epoxy as well as RDL acts as a stress buffer to reduce the stresses in solder joints, therefore the solder ball thermal cycling performance with cu post can be improved significantly. The finite element model of a standard WLP with UBM is also developed for the comparison. The energy dissipation for a standard WLP with UBM is almost twice the energy dissipation for a cu post WLP. This explains that during thermal cycling tests, the cu post WLP is superior in thermal cycling performance to the standard WLP with UBM structure.