| The electrical characteristics of silicon and III-V semiconductors are known to be modified when subjected to mechanical strain. In this work, a four point wafer bending tool is setup to induce mechanical strain in silicon and III-V to study the effect of strain on their electrical performance. The bending tool is initially benchmarked using Si MOSFETs subjected to mechanical strain in order to establish the strain characterization methodology. The effect of strain on performance of Si MOSFETs is modeled for various process conditions and compared with experimental results obtained using the bending tool setup. MOS capacitors on GaAs and Si wafers are also theoretically modeled and experimentally compared to understand the impact of mechanical strain on capacitance measurements. |
