Directed assembly techniques for nano-manufacturing of scalable single walled carbon nanotube based devices

Single Walled Carbon Nanotubes (SWNTs) are being considered building blocks for next generation electronics due to their unique electrical, mechanical and thermal properties. A number of SWNT based devices including scanning probes, field emitters, field effect transistors, biological and chemical sensors, and memory devices have been demonstrated. Despite successful demonstration of these single devices, the success of SWNT based nanoelectronics is hampered due to the lack of a successful nano-manufacturing method. Precise alignment and placement of SWNTs is necessary for successful integration of SWNTs into nanoelectronics.;The work described in this thesis is focused on developing electric field assisted assembly techniques for precise placement and controlled orientation of SWNTs. In a first set of experiments we evaluate the use of micro/nano finger shaped metal electrodes to assemble SWNTs. Eventhough this assembly technique help in understanding the electrophoretic behavior of SWNTs, problems related with orientation, assembly at nanoscale and electrode degradation demanded evaluating alternative techniques.;Nanotemplates that use trenches made in PMMA on a conductive substrate are utilized for the directed, controlled assembly of SWNTs This technique uses a combination of electrophoretic forces and fluidic forces to assemble and align the SWNTs. We were able to assemble SWNTs in trenches that are as small as 80 nm wide and 100,000 nm long over a 2.25 cm2 area in 30-90 seconds. Based on the experimental results and analysis a model is proposed to explain the assembly and alignment mechanism of SWNT s. The technique has been utilized to fabricated interconnects and field effect transistors to demonstrate the feasibility to make devices.;Finally we introduce a novel room temperature assembly technique for fabricating a three dimensional single walled carbon nanotube platform. A top down lithographic approach is used to fabricate the platform while a bottom-up dielectrophoresis method is used to assemble the SWNTs in a 3D architecture. This is a scalable, high throughput and room temperature technique making it compatible with current CMOS technology. We demonstrate the ability to precisely control the density of SWNTs. A finite element model is used to simulate and study the behavior the SWNTs during assembly. We also demonstrate that these structures can be utilized directly as 3D interconnects. Finally, we show that the packaging of these devices, using a conformal pin-free parylene layer, provides a complete process flow for making SWNT based 3D nano-devices.