Designing heterogeneous many-core processors to provide high performance under limited chip power budget | Posted on:2011-07-06 | Degree:Ph.D | Type:Thesis | University:Georgia Institute of Technology | Candidate:Woo, Dong Hyuk | Full Text:PDF | GTID:2448390002458717 | Subject:Engineering | Abstract/Summary: | | This thesis describes the efficient design of a future many-core processor that can provide higher performance under the limited chip power budget. To achieve such a goal, this thesis first develops an analytical framework within which computer architects can estimate achievable performance improvement of different many-core architectures given the same power budget. From this study, this thesis found that a future many-core processor needs (1) energy-efficient parallel cores and (2) a high- performance sequential core. Based on these observations, this thesis proposes an energy-efficient broad-purpose acceleration layer that can be snapped on top of a conventional general-purpose processor. In addition to such an energy-efficient parallel cores, this thesis also proposes different architectural techniques to further boost the performance of sequential computation while those parallel cores are idle. In particular, this thesis develops low-cost architectural techniques to enhance the memory performance of a host core by utilizing those idle parallel cores. This idea is evaluated in two different system architectures: one with the aforementioned acceleration layer and the other with an emerging integrated CPU and GPU chip. | Keywords/Search Tags: | Performance, Chip, Many-core, Power budget, Processor, Thesis, Parallel cores | | Related items |
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