Design of application specific instruction accelerators for multi-standard channel decoding

There is an increasing demand for a portable device to support multiple standards (such as GSM, CDMA, DVB-H) to deliver more services to the customers and to provide seamless connectivity across various geographical regions. The state-of-the-art solutions for multi-standard wireless radio architectures lack to provide computational capability required by the wireless protocols and are not scalable enough to process future standards. In this work, a heterogeneous multi-processor architecture is proposed for multi-standard wireless communication system. Each processor in the proposed architecture is an application specific solution to the particular algorithm or task corresponding to the wireless protocols. Analysis of the computational requirements of channel decoding across various standards shows that the channel decoding is a performance intensive block. Application specific processor architecture is proposed for multi-standard channel decoding. For this processor architecture, application specific instruction accelerators are proposed and designed by analyzing inherent computational parallelism in Viterbi and Turbo decoding algorithms. The proposed instruction accelerators are analyzed using area and timing parameters. The analysis on proposed architecture for channel decoding and instruction accelerators shows that this architecture is highly programmable and scalable to meet computational requirements of channel decoding in the future standards.