A free-space optical solution for the on-chip global interconnect bottleneck: Experimental validation

With the rigorous scaling down of CMOS critical dimensions, emerge several challenges that may signal the end of Moore's law. Although scaling results in devices that are faster and consume lower power, we will run into physical limits as miniaturization persists. It is now widely understood that on-chip global communication poses one such challenge due to issues such as the increasing power consumption and latency in the global wires, which are a direct consequence of scaling. We present optical interconnects as a candidate for relieving the performance bottleneck that metal wires will pose in the near future. A free-space optical inter-connection system has been proposed. The design and experimental validation of the free-space technique are presented.