Study of Electrical Properties of 4Hydrogen-Silicon Carbide/Silicon Dioxide Interface

Silicon carbide (SiC) is a semiconductor material with highly suitable properties for high-power, high-frequency, and high-temperature applications. One of the factors limiting the wide scale implementation of 4H-SiC MOS devices has been the poor quality of SiO2/4H-SiC interface. In this thesis, I have performed an in-depth study of the electrical properties of SiO 2/4H-SiC MOS interface in an attempt to understand the physical mechanisms which limit its inversion electron mobility and investigate the effects of MOS processing conditions. An inversion mobility model, extended from that for silicon, has been used to evaluate the different limiting mechanisms for inversion channel mobility of 4H-SiC MOSFETs. The model is used to predict the ultimate performance and comparison of the performance limits of 6H-SiC vs. 4H-SiC MOSFETs. Process techniques optimized for Si MOS system result in poor 4H-SiC MOS interface with large interface states. Annealing in NO at 1200-1350oC has been shown to passivate the SiO2/4H-SiC interface traps by introducing positive fixed charges but lead to increased carrier scattering. A high temperature oxidation process (1400oC) for thermal oxidation of 4H-SiC has been explored in this research. From 4H-SiC MOS experiments it was found that high temperature oxidation could lead to lowering of surface potential fluctuations and hence lowering of interface charges and surface roughness. Lateral MOSFETs were fabricated on (0001) 4H-SiC substrates using the high temperature gate oxidation process and compared with the commercially used NO annealing process. From MOS-Gated Hall characterization NO annealed sample shows the highest Hall mobility (~60cm2/V.s) with very little charge trapping, while high temperature oxidation and a modified NO annealed MOSFETs have Hall mobility of ~10cm2/Vs and 20cm 2/Vs respectively. The NO annealed MOSFET however is depletion mode and a modified NO anneal process to give enhancement mode MOSFETs do not give significant mobility improvement over high temperature oxidation process. Hall measurements have been used to isolate the effect of carrier trapping and carrier scattering due to different processing conditions. Although, the NO anneal process is successful in passivating interface trapped charges, the inversion mobility is still limited by the Coulombic scattering at low fields due to the charges introduced from the NO anneal and by the surface roughness scattering at high fields. The high temperature oxidation process is also not optimal and has large carrier trapping leading to low carrier mobility due to increased carrier scattering.