Effective distance calculations for on-chip decoupling capacitors in 3-D integrated circuits

On-chip decoupling capacitors alleviate power supply noise at switching nodes by supplying charge during switching activity. Concept of effective distance for decoupling capacitors with a proposed ramp current model is presented. A closed-form expression is derived for effective distance using the proposed model. Proposed model is verified with SPICE simulations and shown to be more accurate than the existing load current model. Analytical results are obtained for 2-D and 3-D ICs with the proposed load current model to highlight the effect of different circuit parameters on effective distance. In 3-D ICs, effect of via-last and via-first/via-middle TSV types is analyzed by modeling electrical characteristics of these TSVs. Electrical models of via-last and via-first/via-middle TSVs are used to obtain analytical results for effective distance. Via-last TSVs are shown to be superior than via-first/via-middle TSVs since via-last TSVs do not rely on metal via stacks to ensure interplane communication. Via-last TSVs require, on average, 7.81% less decoupling capacitance than via-middle TSVs. Effect of number of TSVs, types of TSVs, resistance between decoupling capacitor and load, number of planes, resistance of alternative current path (only for via-first/via-middle TSVs) on effective distance is investigated. These results corroborate the concept of effective distance in 2-D and 3-D ICs which allows use of non-adjacent decoupling capacitors for switching loads. Due to vertical integration in 3-D ICs, effective distance permits the use of a properly sized decoupling capacitor located in one plane for a switching load located within a limited distance in another plane. This advantage leads to die area saving, less layout effort, reduced cost and time to market.