Stochastic Computational Approaches for the Reliability Evaluation of Nanoelectronic Circuits

Reliability is fast becoming a major concern due to the nanometric scaling of CMOS technology. This thesis work initially presents novel computational models based on stochastic computation; in these models, probabilities are encoded in the statistics of random binary bit streams. A computational approach using the stochastic models is then proposed for the reliability evaluation of logic circuits. As it takes into account signal correlations and evaluates the joint reliability of multiple outputs, this approach accurately determines the reliability of a circuit; its precision is only limited by the random fluctuations inherent in the representation of the random binary bit streams. The proposed stochastic approach has a linear computational complexity and is therefore scalable for large circuit analysis. Extensive simulation results demonstrate the accuracy, scalability and execution simplicity of the proposed approach.