Robust Design Techniques for Emerging Technologies of Computing

Conventional CMOS technology used in implementation of computational circuits faces major challenges in continues downscaling. Therefore, researchers explore alternative emerging implementation technologies and alternative computational approaches to overcome these challenges. However, in nanoscale regimes due to atomic scale of devices and poor control in nanofabrication, reliability is a major challenge. In this thesis, we will study reliability issues in crossbar nano-architectures, as an example of alternative implementation, as well as reversible logic, as an example of alternative computational technology.;We study two approaches, namely logic mapping and architectural techniques, to incorporate variation and defect tolerance in crossbar nano-architectures. In the logic mapping approach, different configurations of a logic function on a crossbar nano-architecture are explored to find a reliable configuration which results in better variation and defect tolerance. Simulation results, on a set of benchmarks circuits, show that the proposed method achieve variation tolerance more than 98% of the cases, while in 100% of the cases all defects are eliminated in the mapping. We also use asynchronous design methodologies to propose a self-time crossbar nano-architecture, which allows us to eliminate global clock-like signals (by replacing with local handshake signals) to reduce circuit vulnerability to delay variation. Compared to synchronous counterparts, with around 50% overhead the proposed architecture provides 100% tolerance to delay variations.;In terms of reversible circuits, we study online and offline testing of these circuits as well as fault masking and diagnosis. In order to provide online testing, we use a parity generation methodology to detect faults. This method provides 100% coverage for single fault and more than 99% coverage for multiple faults with 25% fault rate. Furthermore, a cyclic test generation methodology is used to provide test patterns with small amount of test information, applicable for in the field testing. We also propose a set of majority voting gates which can be used in Triple Modular Redundancy (TMR) circuits to enable both fault masking and fault diagnosis. Simulation results show that the average overhead of the proposed majority voters are less than 38% while they provide fault masking and diagnosis.