Clock tree analysis and synthesis considering process parameters and variability

Clock distribution is vital to all synchronous integrated circuits; a poor clock distribution network can result in limited speed, high power consumption, and non-functional circuits. As process dimensions continue to scale, clock distribution faces ever increasing numbers of clock sinks and increased uncertainty in physical and electrical parameters that can significantly limit the yield of manufactured chips. This thesis examines clock tree analysis and synthesis in the presence of process parameters and variation by introducing concepts in statistical analysis, clock tree routing, and clock tree buffer/wire tuning. The efficient statistical analysis techniques developed enable optimization to route and tune variation-aware clock trees. A discretized algorithm for robust clock routing is presented that considers nominally unequal metal layers in addition to metal variations. Then, after the routes are buffered for slew reliability, the buffers and wires are tuned to minimize skew and increase robustness with optional power constraints using heuristics in both the deterministic and statistical timing domain. A novel sensitivity-matching algorithm is presented that allows clock tree skews to be correlated with data-path sensitivies to ameliorate sensitivity to variation. The result from the contributions in this thesis is improved robustness of clock trees in the presence of process variation. Our methods of routing, deterministic tuning, and statistical tuning showed improvements of 32.4%, 24.1%, and 16.3%, respectively, in terms of expected clock skew over traditional algorithms.