Low-power biomedical processors with embedded machine-learning accelerators for analytically-intractable physiological signals

Low-power sensing technologies have emerged for acquiring physiologically-indicative patient signals. However, to achieve high clinical value, it is critical to analyze the signals to extract specific medical information. Given the complexities of the underlying processes, high-order signal models are required for accurate signal analysis. Machine-learning offers distinct advantages, but the computations are not well supported by traditional DSP platforms; high-order models lead to energy and memory intensive computations. This thesis investigates these challenges from the levels of kernel functions, microprocessor architectures, and algorithms.;To enable low-energy computations, a reformulation of a polynomial support-vector machine (SVM) kernel function is proposed that can substantially reduce the real-time computations involved. Using ECG-based arrhythmia-detection and EEG-based seizure-detection applications with clinical patient data, it is shown that the polynomial models yield performance accuracy comparable to the most powerful available transformation (i.e., the radial-basis function), and yet the proposed formulation reduces energy by over 2500x and 9.3 - 198x (depending on the patient), respectively.;Next, an accelerator-based biomedical processor is proposed. It employs a low-power SVM accelerator realizing various kernel functions and reformulations, spanning design points within an accuracy-versus-energy and -memory trade-off space. An active-learning accelerator enables patient-specific model customization while minimizing the modeling effort from human experts. The prototype is implemented in 130nm CMOS. Medical applications for EEG-based seizure detection and ECG-based cardiac-arrhythmia detection are demonstrated using clinical data which reduce energy by 62.4x (273muJ) and 144.7x (124muJ), respectively, compared to a CPU-alone implementation. A patient-adaptive cardiac-arrhythmia detector is also demonstrated which reduces the training data required by a factor of 20x.;While the first IC focuses on discriminative models, a second microprocessor supports a wide range of machine-learning frameworks. It employs accelerators based on kernels that can be combined in structured ways to realize various computations. Memory limitations are also addressed by an embedded compression/decompression accelerator, which reduces the memory footprint by 4x while imposing energy overhead <8%. The prototype IC is implemented in 130nm CMOS. Using six medical applications with real patient data, overall energy savings of 3.1 - 497x are demonstrated with the accelerator-based architecture.