Electrical pre-equalization for high speed optical communication over single-mode fiber

Like all communication channels, optical fibers are not ideal mediums, and they do have their impairments that set a limit on the maximum communication speed they can handle. Driven by the world's growing need for communication bandwidth, progress is constantly being reported in building newer fibers that are capable of handling the rapid increase in traffic.; In this thesis, optical duobinary signalling is combined with a proposed electrical preequalization scheme to extend the reach of a 10 Gb/s system, that utilizes standard single-mode fiber and operates in the 1550 nm band, to several hundred kilometers without any optical chromatic dispersion compensation. In fact, the system reach is influenced by fiber impairments other than chromatic dispersion. The proposed scheme is based on exploiting the linearity of a coherent lightwave system to move the equalization process to the transmitter, where the data is still in its uncorrupted form. More specifically, the duobinary signal is pre-equalized with two tunable T/2-spaced FIR filters. The outputs of the FIR filters then modulate two optical carriers that are in phase quadrature. Thus, the advantages of coherent receiver equalization are still maintained while utilizing a conventional direct detection receiver.; To prove the feasibility of implementing the proposed architecture, a test chip is implemented in a 0.5-mum SiGe BiCMOS technology. The chip incorporates two 10-tap, T/2-spaced FIR filters, which are sufficient to pre-equalize a 10 Gb/s duobinary signal for transmission over distances in excess of 400 km of standard single-mode fiber. Each filter utilizes both edges of a 10 GHz clock to generate the required 20 Gsamples/s. The filters' coefficients are adjustable using twenty 6-bit digital-to-analog converters. The complex pre-equalization capabilities of the chip are tested by post-processing the measured chip output to mimic the effects of the optical channel. In addition, the chip is tested on some electrical test channels. The chip is fully functional at 10 Gb/s, producing results that are in good agreement with those of the system level simulations. The chip occupies an area of 3.2 mm x 3.9 mm and consumes 3 W from a dual supply of 5 V and 3.3 V. (Abstract shortened by UMI.)...