Tuned gate bias transistor

Excessive electric field at the end of the channel of a Field Effect Transistor (FET) causes mobility degradation, results in hot electrons and impact ionization events, generates gate leakage, and leads to breakdown. In the past, a variety of techniques were used to minimize the negative influence of non-uniform and strong electric fields in the second half of a channel, namely, a lightly doped drain, delta doping of the channel, or a field plate positioned behind the gate. Although such methods succeeded to some extent in reducing field strength, further improvement in device performance is possible utilizing field tailoring. With field tailoring, a device with two gates is biased such that Vg1 > Vg2. This results in a more even electric field in the channel of the device which offers a broad variety of improvements. In the current study, a novel heterostructure FET, namely, a pHEMT with a 0.5 mum gate, and a second, longer gate positioned above the first one, is introduced. This second gate is separated by the first gate and the device channel by a thin layer of Si3N 4 enabling separate biasing and therefore field tailoring. The result is a transistor which shows almost constant transconductance, high Early voltage, and improved frequency performance. Comparison through modeling of this novel structure to existing field plate structures is undertaken in this study. Dimensional optimization is also investigated in order to maximize the improvements in transconductance and Early voltage, while minimizing gate capacitance.