Design and analysis of low power SRAM

A static random access memory (SRAM) play a very important role in modern digital VLSI systems. It is an important block in many applicants, such as cache memory, data storage, and microprocessors. Especially, with the development of mobile and high density space applications, digital VLSI systems with low power dissipation are required. As the SRAM occupies the majority area of a chip, reducing the power consumption of SRAM, increasing the SRAM operation speed and minimizing its area are vitally important in memory technology today. First, we look at the scaling trend in the power and speed of SRAMs according to the feature size of a CMOS transistor. We find that when SRAM interconnect delay could be neglected, SRAM delay scales as the logarithms of its size. Then in order to lower the power consumption, we designed a low-power and high-speed SRAM through making the SRAMs operate in a low-power supply voltage to reduce both dynamic power consumption and leakage current concurrently. Finally, we analyzed and designed SRAM circuits with optimal performance parameters such as power and speed by optimizing individual and semi-top blocks of the SRAM for improved energy-efficiency.