Design Techniques for Power-efficient Data Converters in Deep Sub-micron CMOS Technologies

Data converters, including analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and temperature-to-digital converters (smart temperature sensors), are widely used in various areas, since they are the indispensable interface between analog world and digital processing systems. High-level integration in modern IC development makes power consumption a major consideration, especially in the design of data converters that base on power-hungry amplifiers. Furthermore, the developed deep sub-micron CMOS technologies increase the difficulty of realizing high-gain and wide-bandwidth amplifiers with high-efficiency due to gradually decreased feature size and supply voltage.;In this thesis, in order to address the above challenges, two kinds of new amplifier-less techniques for power-efficient data converter design are proposed. To prove the presented concepts, pipelined ADC and smart temperature sensor are developed and fabricated, respectively.;The first design is pipelined ADC using capacitive charge pump and comparator-controlled charging buffer to realize residue amplification. Based on the single-ended topology that verified the proposed idea, the improved differential pipelined ADC has been implemented in a 0.18microm CMOS technology with 0.55mm 2 area. Measurement results show scalable power consumption for sampling rate from 54microW (125kS/s) to 4.94mW (25MS/s) with a signal-to-noise-and-distortion ratio (SNDR) virtually fixed at 52dB. Sampled at 25MS/s, it achieves fine SNDR and effective number of bits (ENOB), which peak at 50.4dB and 8.1-bit, respectively. The SNDR and ENOB keep almost flat at high input frequency, resulting in an effective resolution bandwidth (ERBW) of 36MHz. Under 25MS/s, the ADC records worst DNL and INL of -0.9/1.2 LSB and -1.8/2.5 LSB, respectively. Consistent results are measured for VDD varying from 1.7V to 2.0V on five packaged chips. Under 1.8V supply voltage, the proposed pipelined ADC consumes 4.94mW at 25MS/s and exhibits a Figure-Of-Merit (FOM) of 0.35pJ/ Conv.-step, comparable with other state-of-the-art amplifier-less pipelined ADCs. The designed ADC also features wide power scalability and ERBW, which are not available in other amplifier-less designs. In addition, compared to other power scalable pipelined ADCs, the proposed design has the second widest sampling rate scaling ratio, and its FOM records the best value.;The second design is a novel resistor-based time-domain smart temperature sensor without power-hungry amplifiers. The smart temperature sensor was implemented in a 90nm CMOS technology with 0.18mm2 area. Measurement results indicate that the inaccuracy for tested five samples are bounded from -0.6°C to 0.8°C over -40°C∼125°C after two-mid-point calibration at 25°C and 45°C. When VDD varies from 0.8V to 1.2V, it shows a peak supply sensitivity of 4°C/V after two-mid-point calibration under 0.9V. The sensor dissipates 11.8muW under a sampling rate of 5kS/s and a counter reference clock of 20MHz from a 0.9V voltage supply. The resulted FOMs are comparable with the state-of-the-art sensors. It also records the lowest supply voltage in the literature, expands the temperature range of resistor-based sensors by 65%, and is simple and easy to implement.