A framework for FPGA-based acceleration of neural network inference with limited numerical precision via high-level synthesis with streaming functionality

Deep neural networks (DNN) are achieving state-of-the-art performance in many artificial intelligence tasks, such as computer vision and speech recognition. Due to the high computational requirements of DNN, there is an increasing need to design custom hardware for accelerating the DNN computation with a low power budget.;This thesis proposes an FPGA-based acceleration solution for DNN inference, realized on a SoC device where software controls the execution and off-loads compute-intensive operations to the hardware accelerator. To minimize the hardware cost, limited precision data representations are investigated for DNN computations, and incorporated in the accelerator design. Streaming functionality is added to the LegUp high-level synthesis tool, allowing the hardware accelerator to be designed entirely in C-language and synthesized to pipelined hardware. The accelerator solution is not tied to a particular DNN architecture; rather, it is configurable in software, permitting the acceleration for a range of DNN architectures proposed in recent literatures.