Analysis and simulation of packet conditioning in diffserv architecture

In the first part of the thesis, we discuss in detail the main component of a traffic conditioning block, i.e., traffic meters. We propose a new approach to efficient packet metering, which processes incoming packets in small groups rather than packet-by-packet. To overcome the problem of a low-resolution clock and the overhead of reading the clock frequently in microprocessor, we also propose a new method of measuring time to regulate the operations performed by the traffic meters. Our use of one-time debit in implementing standard meters, such as the average rate and token bucket meters, makes them more faithful to the prenegotiated transfer rate and burst size limit.; In the second part of the thesis, we developed simple simulator running on Intel based micro-processor with Microsoft Windows ($M$PSimulator). Using $M$PSimulator, we demonstrate that our implementation of traffic conditioning algorithms can process packet headers at high speed. Provided the transmission of the packet bodies can keep pace with packet header processing, we can achieve a transmission rate of over 10 million packets/sec. Such a speed is a few times larger than known traffic conditioning block algorithms. The simulation on microprocessor provides basic data needed for general simulation using OPNET simulator and OPNET simulation study evaluates the performance of our implementation in more realistic network environment. Simulation demonstrates that our implementation of DS packet forwarding does enforce QoS specified by the DS code. We conclude that the currently available microprocessor hardware intended for desktop computing is adequate for traffic conditioning in a diffserv enabled Internet router at a speed up to 10 million packets per second. (Abstract shortened by UMI.)...