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Fault diagnosis techniques for deep submicron technology

Posted on:2002-07-16Degree:Ph.DType:Thesis
University:The University of Texas at AustinCandidate:Ghosh Dastidar, JayabrataFull Text:PDF
GTID:2462390011996209Subject:Engineering
Abstract/Summary:PDF Full Text Request
The first part of this dissertation investigates techniques for delay fault diagnosis. With the advent of deep submicron technology and more aggressive clocking strategies, delay faults are becoming more prevalent. Diagnosing delay faults is essential for improving the yield and quality of integrated circuits. Given that a circuit has failed to meet its timing specifications, this work proposes new techniques to efficiently diagnose the cause of the faulty behavior. The techniques proposed in this thesis aim to reduce the search space for direct probing techniques like E-beam probing. Also a ranking strategy is proposed to guide the direct probing techniques. Procedures are described for adaptively generating additional test vectors to improve the diagnostic resolution for delay faults. A defect type of growing importance is bridging defects. A diagnostic technique is proposed for diagnosis of bridge faults that can potentially cause delay failure. As a result of the greater densities and more aggressive clocking strategies, FPGAs have become more susceptible to delay faults. An FPGA differs from a general integrated circuit in its capability for reconfiguration of the logic in the circuit-under-test (CUT). This unique feature is exploited in a very systematic and efficient way in the proposed method to arrive at a more precise set of suspects.; The latter part of this dissertation focuses on fault diagnosis techniques for built-in-self-test (BIST) environment. Diagnosis in a BIST environment adds an extra level of difficulty in comparison to diagnosis in a non-BIST environment. This is because it is first necessary to find out from the collected information which scan-elements have captured faulty responses and which vectors have produced a faulty response. This dissertation proposes a robust and low hardware overhead technique that can identify any number of failing scan cells. Finally, a novel technique for diagnosis is presented that allows non-adaptive identification of a subset of the failing test vectors. Innovative pruning techniques are used to efficiently extract information. While not all the failing BIST test vectors can be identified, results indicate that a significant number of them can be. This additional information allows faster and more precise diagnosis.
Keywords/Search Tags:Diagnosis, Techniques, Delay
PDF Full Text Request
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