Architectural and register-transfer-level power analysis and optimization

This thesis focuses on architectural and register transfer level analysis of power consumption and optimization of power optimization.; First, a statistical framework for RT-level power analysis is introduced where two new power macro-modeling techniques are proposed: the sampler macro-modeling based on the sampling theory and the adaptive macro-modeling based on the regression analysis. Experimental results demonstrate that compared to census macro-modeling, sampler macro-modeling reduces the simulation time by an average factor of 50 while the adaptive macro-modeling lowers the estimation error by an average factor of 16.; An architectural macro-analysis technique for evaluating the power dissipation of application programs running on a high-performance microprocessor is presented next. The proposed technique uses architectural simulation of the target processor under typical input stream to extract the characteristic profile of the processor. The profile is then used to automatically synthesize a new program with much shorter instruction trace, but the same characteristic profile, which is then simulated using an RT-level simulator. Experimental results show the high accuracy (i.e. within 2% error) of the proposed technique applied to an Intel Pentium processor running SPEC int 95 benchmarks.; An architectural power micro-analysis technique for accurate calculation of the power dissipation induced by a certain instruction running on a target processor. The proposed algorithm automatically attributes the power consumption of each gate within the processor to the instructions that are being executed in the instruction pipeline or instruction execution queues. As a result, the power micro-analysis enables the processor architect or designer to identify the instructions that waste power or consume a lot of power.; Finally, we propose a split-bus architecture for low power. The basic idea is to split a monolithic shared bus into two or more parts so as to reduce the effective switches capacitance per data routing through the bus architecture. This is achieved by formalizing the bus splitting for low power and heuristically solving the resulted NP-hard problem. Experimental results show that the power saving of the split-bus architecture over the monolithic-bus architecture can be as high as 50%.