Yield estimation based on layout and process data

The project deals with the estimation of Integrated Circuit (IC) yield based on layout and process characterization data. It emphasizes the need to design for manufacturability, and the importance of assessing the quality of the design, to improve the manufacturability of the IC, and thereby reduction of cost. The report outlines innovative and robust CAD techniques developed to predict the yield of any given integrated circuit at the schematic stage, as well as the layout stage using Cadence EDA (Electronics Design Automation) tools. The interconnect yield model, which is a critical area-based yield model is applied for estimating the yield of any given integrated circuit. The different yield loss mechanisms are analyzed, with concentration on the functional yield loss due to spot defects, including shorts and opens. The vital concept of critical area is applied for yield estimation, and an improvised CAD technique (Cadence Dracula(TM)) is established to extract the critical area for shorts in metal lines of the same conducting layer as well as different layers due to the defects in the oxide separating the layers, and also opens in any given IC layout. A C++ code is written to extract the parameters from the schematic of any IC design and calculate the interconnect yield. A user-friendly Applet viewer is designed using JAVA to estimate the yield for any given integrated circuit at the layout stage, using the layout in the GDSII format as input. The results of critical area extraction and yield estimation for an ideal test circuit designed using Cadence are presented. The project concludes with a description about different yield enhancement techniques to improve the manufacturability of the IC.