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On methods to improve test generation efficiency and test response compaction

Posted on:2004-01-12Degree:Ph.DType:Thesis
University:The University of IowaCandidate:Wang, ChenFull Text:PDF
GTID:2468390011467068Subject:Engineering
Abstract/Summary:
In this thesis, we present new design-for-test (DFT) techniques for high quality and low cost VLSI testing. Specifically, we propose techniques to improve deterministic test pattern generation, to efficiently identify redundant faults in combinational logic circuits and to design space compactors.; The first topic considered in the thesis is to improve the ability of automatic test pattern generators (ATPG) to resolve hard-to-resolve faults in designs. We propose four new ATPG techniques that target to improve the four main components of ATPGs. Specifically, Dynamic Decision Ordering is used for better backtracking, Conflict Driven Recursive Learning helps justify decisions that are hard to justify, Conflict Learning improves implication procedure and Blockage Learning can efficiently guide fault effect propagation. The first three proposed techniques are characterized by conflict driven. This feature makes the proposed techniques efficient and effective. With the proposed technique, we achieved to resolve all the faults in larger ITC'99 benchmark circuits and some industry designs.; Redundant faults in logic circuits may cause many undesirable problems. It is important to identify redundant faults with efficient procedures. In this thesis, we propose a fault oriented redundant fault identification procedure called REDI. The fundamental idea of REDI is to identify redundant faults by proving that no paths from the fault to primary outputs are sensitizable. To efficiently enumerate all paths from a fault, REDI uses partial path analysis. On top of the basic procedure, REDI also uses blockage learning, dynamic branch ordering and fault grouping techniques to improve the efficiency. Experimental results show that REDI can identify a majority number of redundant faults in ISCAS and ITC'99 benchmark circuits.; The last part of the thesis introduces a new class of test data compactor designs. This class of compactors have finite memory exhibiting finite impulse response. Two types of compactors called block and convolutional compactors belonging to this class are investigated. The new compactors can achieve any desired compaction ratio while tolerating unknown values in test responses and support fault diagnosis.
Keywords/Search Tags:Test, New, Improve, Fault, Techniques, REDI, Compactors, Thesis
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