Analysis and optimization for global interconnects for gigascale integration (GSI)

The main objective of this thesis is to develop new interconnect-centric methodologies to optimize global interconnects in a GSI chip. A length-independent optimal wire width is rigorously found that simultaneously maximizes data flux density and minimizes latency. Data flux density is the product of interconnect bandwidth and reciprocal pitch and represents the number of bits per second that interconnects can transfer per unit width. Other cross-sectional dimensions are also optimized to minimize crosstalk, energy-per-bit and the dynamic delay variation caused by different switching patterns. The optimization process is based on novel compact physical models that are derived in this thesis for latency and crosstalk of co-planar distributed RLC lines. Rigorous physical models are derived for multi-level crosstalk noise that take into account virtually all near as well as inter- and intra-level far aggressors. These models prove that crosstalk remains small and constant in all generations of technology if optimal wire dimensions are utilized. Chip-package co-design methodologies are also developed that show the optimal partition between chip-level and package-level signal and power distribution. Finally, the lengths beyond which optical waveguides can outperform electrical wires in terms of data flux densities are identified for various technology generations.